Flash memory FLASH is a fast-erasable non-volatile memory, and it has developed very rapidly since Intel Corporation introduced FLASHMemory technology in 1988. The characteristic of FLASH is that it can keep the stored information for a long time without power on. In addition, it also has the characteristics of not requiring storage capacitors, higher integration, lower manufacturing cost than DRAM, convenient use, flexible reading and writing, fast access speed, and low power consumption. Based on actual issues, in a DSP-based voice processing system, starting from these important indicators to measure the superiority of the voice processing system such as storage capacity, storage time, playback sound quality, etc., FLASH is selected as an off-chip memory to realize voice data Digital recording and playback not only ensure the high performance of the system, but also reduce the system cost.

1 system composition

The actual system is a bus-type network based on DSP, and each unit uses TMS320F206 digital processing chip as a microprocessor to realize voice transmission, recording, storage and playback. The block diagram is composed as shown in Figure 1.

In the system, both the voice data collected by the sound card and the data transmitted from the network card can be stored in FLASH. As the stored digital information, the data will not be lost and distorted, so it will not introduce any noise. The memory used by this system is two 4M-bit FLASH, and the recording time is more than 2 minutes.

2 DSP and FLASH interface circuit design

2.1 Introduction to the chip

The DSP used in the system is the TMS320C2XX series, which is a 16-bit fixed-point arithmetic digital signal processor introduced by TI. It is extremely cost-effective and has become an ideal substitute for single-chip microcomputers. It has been widely used in communications, voice processing, military, instrumentation, image processing and other fields. The memory used by the system is a FLASH chip produced by AMD, the model is Am29F040B. Its capacity is 512K×8bit, and the storage time provided is 55, 70, 90, 120 and 150ns, so there is basically no waiting time when high-speed microprocessors (such as DSP) operate on it. In order to avoid bus competition, the device has independent chip select, write enable and output enable control. The device command set conforms to the FLASH standard of JEDEC single power supply. It can be controlled by writing the FLASH command register with a standard microprocessor writing sequence. operating. Am29F040B has a power saving mode. Entering this mode when FLASH is not in use can greatly reduce power consumption. Am29F040B can also be operated in sectors. The default is divided into 8 sectors, each with a capacity of 64K bytes.

2.2 Interface circuit design

The design of the interface circuit mainly considers the allocation of the memory address space and the timing requirements for writing and reading. in the system? A total of 1M address space is required. We use two FLASH, and the DSP has only 16 address lines, which can only provide 64K addressing space, so it must be used in paging to allocate the address space reasonably. To this end, we divide the storage space of each slice into 32 pages, each with 16K bytes. The address of each page of slice A is from #8000h~#0bfffh, and the address of each page of slice B is from #0c000h~#0ffffh. Based on the above analysis, the interface circuit between DSP and FLASH is shown in Figure 2.

In the figure, only the interface circuit between DSP and one FLASH is drawn, because the other one is similar, but different chip selections are obtained through different decoding. DSP selects paging with D0~D4, and A12~A15 allocate the addressing space of two FLASH through appropriate decoding.

3FLASH programming method

Various operations can be implemented on FLASH by writing a specific command or command sequence to the FLASH command register. Table 1 provides the definition of valid commands. If the written address and data values ​​are incorrect or the written sequence is incorrect, the device will be reset to the read array data state. In the table, except xxx refers to any value, other values ​​are all hexadecimal numbers, RA refers to the memory address to be read, RD refers to the data to be read, PA refers to the address programmed into the memory, and PD refers to the address programmed into the memory data. During programming, the address is locked on the falling edge of WE# or CE#, and the data is locked on the rising edge of WE# or CE#. SA refers to the sector address.

Table 1 shows the definition of all operation commands. In this system, DSP mainly uses read, refresh and programming operations to control FLASH, which will be explained separately below.

3.1 Read array data

The read operation is very simple, only one bus cycle is required to directly read the data of the FLASH corresponding unit. After power-on, the device is automatically in the state of reading array data? After the refresh and programming operations are completed, the device is also in the state of reading array data? Writing a reset command to the device can also reset the device to the state of reading array data. The read operation is mainly used for playback of recorded content.

3.2 byte programming command sequence

The programming command is more complicated, and each unit write requires four bus cycles. The first two are unlock commands, followed by programming setup commands, which are the address and data to be written to the unit. Figure 3 is the basic flow of the programming operation.

How to judge whether it has been written correctly? An embedded programming algorithm is provided inside the device, and the programming operation status can be known by querying the DQ7 or DQ6 bit. After the embedded programming algorithm is completed, the device automatically returns to the read array data state, and the address is no longer locked. Byte programming commands are the basis for recording. What needs to be pointed out here is that: during programming, you can't change any bit of the memory cell from "0" to "1", only the refresh operation is possible. Therefore, after a certain section of the FLASH storage area has been recorded, if it is not refreshed, this section of storage area cannot be recorded.

3.3 Chip refresh command

The chip refresh operation requires 6 bus cycles. The first two are still unlock commands, then refresh setup commands, and then two additional unlock write cycles, which are chip refresh commands. The difference between the refresh operation and the programming operation is that the refresh operation is completed for the entire chip, while the programming requires writing unit by unit. Of course, if you do not want to refresh all the chips, you can use the sector refresh command. Whether the refresh is complete or not can also be judged by querying the DQ7, DQ6 or DQ2 bits. Figure 4 shows the refresh operation flow.

Both programming operations and refresh operations require data query, collectively referred to as write operation status query, to determine whether the write operation has been completed correctly. Am29F040B provides DQ2, DQ3, DQ5, DQ6, and DQ7 bits for querying the write operation status. Table 2 shows the functions of these bits.

Different bits can be queried according to the specific situation. It should be noted that when using DQ7 and DQ2 to query status information, an effective address is required, and if the DQ5 bit is read as 1, it means that the programming or refresh operation has exceeded the timing limit. In the author's actual application, the programming operation queries the DQ7 bit. When the read DQ7 bit is consistent with the written DQ7 bit, it means that the write is successful and you can continue to write a unit; during refresh operation, query whether any unit (usually take a unit) is 0FFh, if it is, then The refresh is completed correctly.

After solving the hardware interface circuit of DSP and FLASH and the software programming method of DSP to FLASH, through appropriate program control, the digital recording and playback functions of the system can be realized. It can record the voice data received in the DSP network, or record the speaker's voice through sound card sampling. The system is applied to the speech classroom, can smoothly realize the follow-up and re-reading of the student computers, and as long as the recording content is not refreshed, it will not be lost even if the power is off. In other electronic products, this method can also be effectively applied.

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